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Method of Testing Global Wires Used in Wafer Scale Integration

IP.com Disclosure Number: IPCOM000060732D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Sandoval, A Turnbull, JR [+details]

Abstract

This article describes a method of testing global wiring used in "wafer scale" integration (i.e., an entire wafer forms one "chip"), or in very large-scale integration (i.e., one wafer contains only 2-4 "chips"). Global wiring" refers to the wiring which interconnects the input/output (I/O) pads of each "domain" (i.e., functional block) and connects these domain I/O pads to wafer I/O pads. Testing the continuity of this global wiring is facilitated by creating an additional level of temporary wiring (i.e., a layer of insulation with via holes to all pads and a patterned layer of metal on the insulation layer) which interconnects a selected large set of the global wires in series by interconnecting selected domain I/O pads.