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High-Speed CMOS Shift Register Latch

IP.com Disclosure Number: IPCOM000060764D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Loehlein, WD [+details]

Abstract

The proposal describes means for considerably improving the switching speed of a shift register latch. To this end, the latch pull-up transistors are operated dynamically. Dynamic operation takes place only during transition and is determined by an R/C configuration. The figure shows a latch with transistors T1...T4 and input/output nodes NT and NC. Such a latch constitutes a conventional CMOS latch, as is used, for example, as a master latch in conjunction with a slave latch in multiport latch arrays. An output driver input and the slave input capacity are assumed to impose a high capacitive load on nodes NT and NC. For switching the latch via one of the nodes NT and NC, the capacitance of the respective node has to be discharged along the paths indicated by transistors T5...T10.