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Cmos Multi-Way and Logic Disclosure Number: IPCOM000060767D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09

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Loehlein, WD Mueller, R [+details]


Proposed is a circuit implementation, by means of which logic circuits with a plurality of inputs may be obtained without (noticeably) impairing the switching speed. This is essentially accomplished by a low- ohmic, sense circuit triggered discharge path which is provided parallel to the input chain. Fig. 1 shows a conventional 4-way AND gate, at whose output a logic "1" occurs if all inputs A, B, C, D are "1". In that state, all (P-channel) transistors T1 to T4 are off, and node A is discharged by series-connected (N-channel) input transistors T5 to T8. As this series connection mainly influences the circuit delay, the number of inputs provided is in most cases limited to, say, four. In the proposed circuit (Fig. 2), two series-connected transistors T5/T6 are provided in parallel to the actual discharge path T2...