Pipeline Control Structure for Processor Unit
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09
This article describes a pipeline control structure for a processor unit (PU) wherein each chip in the processor unit generates its own controls internally. Cycle time is reduced because delays due to controls having to cross chip boundaries are eliminated and successive control registers are in close proximity. I/O pins on the chip previously required for controls are free for other needed functions. In the present disclosure a four-stage pipeline control structure is utilized. In implementing this control structure, each chip in the PU will provide most of its own controls internally. Each chip contains a series of control registers and control logic, each controlling a different phase of instruction execution and the hardware registers used in that phase of execution.