Time Sharing of System Data Bus During Storage Head Cycles
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09
This article describes a time sharing of a system data bus during storage read cycles which reduces system data bus utilization and increases processor performance by doing two operations in the time normally required to do one operation. In computer systems, there is frequently an interconnection of various units of the system by the use of common addresses and data busses. To transfer information between the various units of the system, there is usually a well-defined set of sequences involving control signals, the address bus, and the data bus to determine which unit will get control of the busses next and how the information will be transmitted. In many cases the busses between the units are highly utilized and may become a bottleneck that limits the overall system performance.