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Fast Memory Test for Diagnostics Disclosure Number: IPCOM000060796D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09

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Scott, SM [+details]


This article is a description of the "Fast Memory Test for Diagnostics" algorithm used for performing an exhaustive data test of memory with an Error Correcting Code (ECC) system. This algorithm requires that the memory hardware have the ability to flag the central processor when an uncorrectable error has occurred. The memory is tested by writing a specific set of bit patterns to memory and then reading them back. It is not necessary to compare the bit patterns read back with the bit patterns written to memory. The ECC system will detect an error that it can not correct and flag the central processor. After a segment of memory has been tested, the central processor can test for any errors that occurred within that segment simply by querying the error flag set by the ECC hardware.