Browse Prior Art Database

Fault-Tolerant Control of Access to Shared Data in Cached-Dasd Storage Systems

IP.com Disclosure Number: IPCOM000060833D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Benhase, MT Schimke, SW [+details]

Abstract

When two host processors share data, a processor which is updating a portion of that data must prevent the other processor from concurrently reading or updating that portion. A cached-DASD (Direct-Access Storage Device) storage system includes two storage directors (controls) which share data in a memory called subsystem storage or cache. The subsystem storage hardware includes a register shared by the two directors and called the Test and Set Register (TS). This register has hardware tie-breaking so that only one storage director may "own" TS at one time. TS is used as a lock to protect a structure called the directory; by convention, a storage director cannot access the directory before accessing TS. When TS is not available after a preset elapsed time, caching operations are limited to preserving integrity.