Leakage and Noise Protection by Broadside Early Spill of Zero Cells
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09
In Shared Word Line (SWL) Random-Access Memory (RAM) arrays, cells written to "zero", e.g., at cell node 4, can leak, couple or be written to a lower than desired voltage. These cells could interfere with reading a "one" stored in a cell on the same bit line. To avoid these problems, this circuit utilizes the standby portion of the cycle to simultaneously cause any cells written to a weak level zero to spill charge and adjust them to a predetermined level. This level is selected to be sufficient to adequately isolate all the cells which were written in the zero state. The circuit shown provides charge sharing between word lines as follows: The unhook signal is brought low, which floats the couple node.