Browse Prior Art Database

Dynamic RAM Refresh Controller

IP.com Disclosure Number: IPCOM000060849D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Cook, TE [+details]

Abstract

A dynamic random-access memory (RAM) 1 requires a periodic refresh of its storage cells. Each RAM cell must be refreshed at least once per interval T (one millisecond). If there are N (128) refresh cycles needed to refresh all cells of the dynamic RAM, then the refresh access time must be at least once every t=T/N (8 microseconds). The overall concept is to perform a refresh operation at least once every eight microseconds; however, if the RAM is not being used, then perform a refresh during every address bus cycle time. The counter 2 is incremented every time a refresh operation occurs, and the value of the counter is used as the address for the next refresh of the RAM 1.