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Technique to Improve Field Replaceable Unit Isolation for Large Systems

IP.com Disclosure Number: IPCOM000060900D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Messina, BU Tendolkar, NN [+details]

Abstract

This hardware checking technique reduces the number of field replaceable units (FRUs) implicated when an error occurs. As shown in the figure, error signals S1,S2,...,Sn are generated on FRU A, and latched up on FRU B in latches C1,C2,...,Cn, respectively. Also Y, the logical OR of signals S1,S2,...,Sn is generated on FRU A and sent to FRU B where it is latched in latch R. Two error syndromes can then be used to determine the FRU or FRUs in error. Syndrome 1 If any latch Ci is on and R is on, then FRU A is an error. Syndrome 2 If any latch Ci is on and R if off, or R is on but the Ci's are off, then FRU B and the board containing FRU A and Bcan also be in error.