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Fast Read-Out of Twin Four-Square Array by "Local Potential Equilibration" Disclosure Number: IPCOM000060916D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09

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Related People

Brigida, DJ Lee, HS [+details]


A choice of new operating conditions is described for a twin 4-square memory cell [*] which results in immediate localized equilibration of the stored charge. This mode of operation has the advantage of improved performance, with the position of the cell not being relevant to performance. As shown in Fig. 1, which is a sectional view taken through a word line 10 of a twin 4-square memory cell, a first storage capacitor 11 which includes a bit/sense line left BSL and a first N diffusion region 1 having a thin dielectric layer 3 interposed therebetween and a second storage capacitor 12 which includes a second bit/sense line right BSR and a second N diffusion region 2 also having layer 3 interposed therebetween. Regions 1 and 2 are disposed at the surface of semiconductor substrate 20 made of P type material.