Byte-Wide Implementation of RLL (1,7) Code
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
The run-length-limited (RLL) (1,7) encoding algorithm, as defined, generates three encoded bits for each two data bits. The implementation shown herein allows simultaneous encoding of an entire byte. This has such advantages as permitting a portion of the logic to operate at 1/4 speed; requiring register REG1 to parallel load only and not shift; and enabling two of the state latches to be made to be equal to two bits from the preceding data byte which eliminates the next state logic for these latches. This last feature is also attractive if a wrap check is included, since the latches may already exist in the design. Twelve encoded bits are generated at a time and consequently register REG2 must contain 12 latches.