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Multiple Frequency Data Clock Using Phase-Locked Loop Disclosure Number: IPCOM000060924D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09

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Gillingham, RD [+details]


This article describes a circuit for synchronizing a logic clock signal to one of several possible data frequencies when reading data from external media. The figure is a block diagram of the circuit to be described. A phase-locked loop locks the phase of an output clock, STDCLK, to read data signals, RDATA, typically from a diskette unit. The circuit includes features to operate with several units having different data rates. Charge-pumped, phase-locked oscillators with bandwidth controlled charge pump and loop filters including output dividers are described in the prior art [1]. Selecting different data rates involves changing the frequency of a VCO 14 and the period of a one-shot multivibrator 20. The function of the one-shot (20) can be performed by other types of circuits, e.g., delay circuits.