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Variable Start Location Circuitry for a Display Ram Secondary Port Shift Register Disclosure Number: IPCOM000060940D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09

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Gray, KS [+details]


An enhancement for a two-port Display-RAM (D-RAM) is described in which each stage of the parallel-loaded secondary port shift register is made independently accessible. Each of the shift register stages (S.R.S.) are capable of being independently coupled to a common data input/output bus in response to a plurality of decoders, in turn, responsive to a serial data start address. Circuitry that allows any bit in a D-Ram secondary port shift register string to be the first bit for both reading and writing is shown in the figure. With the circuitry (within the dashed line enclosure) repeated between register (S.R.S.) pairs at each potential starting point, all bits can be rippled through. Steering transistors T1, T4, and T5 and a register bit decoder (RBD) 2 are required for each possible starting position.