Browse Prior Art Database

Multi-Function FET I/O Masterslice Cell

IP.com Disclosure Number: IPCOM000060954D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Fitzgerald, JM [+details]

Abstract

Masterslices allow semiconductor wafers to be processed up to the personalizable levels and then stockpiled. Use of masterslices provides a significant reduction in the "turn around time", the time it takes to fabricate a part. An input/output (I/O) cell for a CFET (complementary field-effect transistor) masterslice chip can be personalized with a first metal layer alone to implement any one of six functional configurations. Two metal layers may be used for global wiring between cells and for power distribution. Each configuration can have either of two different power levels. Present CFET or CMOS technology has 12 mask levels with 2 levels of metal, so that the masterslice concept becomes practical for FETs as well as for bipolar technology. Fig. 1 shows the schematic of the masterslice for the I/O cell.