Browse Prior Art Database

Dynamic Logic Array

IP.com Disclosure Number: IPCOM000060959D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Bonetti, B Tarolli, A [+details]

Abstract

The circuit is a software alterable programmable logic array (PLA) with additional alterable input and output functions. Personalization is achieved (see part (A) of the drawing) through the provision of a shift register latch (SRL) 10 and a logic switch (LS) 12 at each node of the AND array 2, OR array 4, and any other programmable nodes, such as the programmable input function (PIF) 6 or programmable output functions (POF) 8 of the PLA. The SRL 10/LS 12 combination is analogous to the fusible link in a standard fusible programmable logic array. The SRL 10 controls the LS 12. The SRLs 10 are connected in one serial scan path throughout the entire module. In the AND array 2, a "1" programmed into the SRL 10 causes LS 12 to transfer the output of decoder 14 to product term node 16.