Browse Prior Art Database

Hiding of Store Protection Checks in a Pipelined System

IP.com Disclosure Number: IPCOM000060971D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Buterbaugh, EW Kogge, PM Olnowich, HT Vandling, GC Watson, LA [+details]

Abstract

In a pipelined system, store protection checks prior to a store operation often add an extra cycle to the store time. During this extra cycle, checks are made on the addressed location to determine if a write to that location is a valid operation. The checks usually involve the reading of a memory location (either the location to receive the store data or a location in an auxiliary memory), and therefore cannot be performed in the same cycle as the store operation without increasing the cycle time. If the store protection check is executed in Cycle 5, seen in Fig. 1, immediately prior to the store cycle, Cycle 6, it adds an extra cycle to the store execution time. It is possible to hide this additional cycle in pipelined central processing unit (CPU) systems having operand prefetch.