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# Algorithm to Make Test Generation Smart Remade Decisions

IP.com Disclosure Number: IPCOM000060982D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 59K

IBM

## Related People

Shearon, PC: AUTHOR

## Abstract

The application of an algorithm to the computer program Enhanced Test Generation (ETG) increases test coverage and reduces running time for generating tests on logic circuits. During test generation on logic circuits the algorithm makes smart remade decisions when two unique situations occur, as opposed to always remaking the highest decision. In the first situation, during test generation for an objective, when it is absolutely necessary for a block to be at a certain value ("core" value) but it is also absolutely necessary for the same block to be at a different logic value ("core" value), stop processing because it is not possible to generate a test.

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Algorithm to Make Test Generation Smart Remade Decisions

The application of an algorithm to the computer program Enhanced Test Generation (ETG) increases test coverage and reduces running time for generating tests on logic circuits. During test generation on logic circuits the algorithm makes smart remade decisions when two unique situations occur, as opposed to always remaking the highest decision. In the first situation, during test generation for an objective, when it is absolutely necessary for a block to be at a certain value ("core" value) but it is also absolutely necessary for the same block to be at a different logic value ("core" value), stop processing because it is not possible to generate a test. In the second situation, when a block is at a logic value that is not absolutely necessary to generate a test for an objective, but for the same block a different logic value is absolutely necessary ("core" value), then the decision on which the original logic value was assigned should be remade. The algorithm is implemented in ETG as follows. Expand a block by creating its come from and go to "N", "D", "C" or "CD" blocks, as seen in the flow chart in Fig.
1. Process a block, possibly changing it to a "D" or "CD" block, as seen in flow chart in Fig. 2. Assign the "N", "D", "C", or "CD" block's logic values including the "core" value, as seen in Fig. 3. Resolve conflicts by remaking decisions on the "N", "D", "C" or "CD" block based on the original logic "cor...