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Charge Pump Circuit for a CMOS Substrate Generator

IP.com Disclosure Number: IPCOM000060989D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
DuPasquier, MP Piro, RA [+details]

Abstract

A circuit is described for a substrate generator in an n-well, complementary metal oxide silicon (CMOS) technology. This circuit generates a negative bias for the p-type substrate. The advantages of this implementation over the conventional approach are 1) a higher efficiency of charge transfer to the substrate, i.e. reduced losses in the transfer diodes, and 2) reduction of minority carrier-induced latch-up. Fig. 1 is the circuit diagram. Fig. 2 is the timing chart of the driver output signals X and Y, while Fig. 3 shows the voltage level on nodes A and B on a corresponding time scale. The oscillator 2 provides a signal to the driver circuit 4 which provides two out-of-phase signals X and Y to drive a charge pump 6.