Browse Prior Art Database

Dual Etch - Dual Insulator to Eliminate Defects

IP.com Disclosure Number: IPCOM000060991D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Gati, GS Niermann, DL [+details]

Abstract

Interlevel shorts between successive levels of chip metallization are mainly of two major defect types: photo-related and particle-related. The use of composite insulators eliminates many of the particle-related defects but not the photo-related (pinhole, etc.) defects. A previously proposed sequence of process steps to eliminate both types of defects consisted of: 1. Deposition of SiO2 . 2. Etching of vias. 3. Deposition of plasma nitride. 4. Re-etching, using a blockout mask, to remove nitride in via areas. Electrical testing done on test vehicles made with this process flow resulted in high voltage ramp fails in regions of pinholes in the SiO2 covered with the plasma nitride.