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CMOS Supply Sequence Circuit

IP.com Disclosure Number: IPCOM000061003D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Penoyer, RF [+details]

Abstract

A circuit is described which assures that complementary metal oxide semiconductor (CMOS) n-wells are sufficiently biased relative to p- channel source/drains to prevent forward biasing of junctions. The circuit shown in Fig. 1 operates (with typical voltage levels of: high supply voltage (VH) = 5 volts, n-well supply voltage (Vnw) = 6 volts, substrate supply voltage (Vsub) = -1 volt; and threshold voltage of n- channel transistors (VTn) = 1 volt @ source-to-substrate voltage (Vs-sub) = -1 volt and VTn = 1.7 volts @ Vs-sub = -6 volts) as follows: 1. VH and Vnw supplies come up, charging n-well bus Nwb through the impedance Z of the Vnw supply and high supply bus VHb through the source follower, transistor N1. Transistor N1 maintains on VHb a voltage of one VT below the n-well bus potential. 2.