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Delay Block for CMOS Drams

IP.com Disclosure Number: IPCOM000061010D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Parent, RM Scheurlein, RE [+details]

Abstract

A function "replica" plus a controlled delay block is inserted in the timing chain of complementary metal oxide semiconductor (CMOS) dynamic random-access memory (DRAM) to ensure that the circuit is functional so that the circuit can be characterized while minimizing circuit performance impact. The method is used especially in early design to determine the minimum necessary delay to incorporate in a final function replica design. The block diagram (Fig. 1) shows the insertion of the variable delay D after the conventional function "replica" delay block R1 between clocks C1 and C2 of the timing chain for functions F1 and F2. The variable delay D is comprised of the series of inverters I1, I2, I3 and NAND circuits N1 and N2, as shown in Fig. 2.