Inhibit Sequencing Delay Circuit
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Electrical noise created during VLSI chip testing may be controlled by keeping off-chip drivers inhibited until applied conditions of test are completed. The drivers are then 'enabled' in groups, with a sequencing delay between groups, to take a test measurement. This is followed by the drivers being inhibited in groups with a sequencing delay between groups. This article discloses a circuit for providing significant delay, utilizing a small area on the VLSI chip, for the purpose of off-chip driver 'inhibit' and 'enable' sequencing. The delayed inverter circuit shown in Fig. 1 is organized into a sequencing network providing symmetrical sequencing delays for 'inhibit'/'enable' functions and requires only a single 'inhibit' input chip pad.