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Universal Asynchronous Receiver Transmitter Data Loss Detection Arrangement

IP.com Disclosure Number: IPCOM000061019D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Brown, JN Smolen, MS [+details]

Abstract

A method is described to detect the loss of data when using the asynchronous communication card of the IBM Personal Computer (PC). Under normal conditions, a data character transmitted to the universal asynchronous receiver transmitter (UART) is assembled as a complete character when a start bit, 5-8 data bits, an optional parity bit, and a stop bit is received. The data bits are transferred into a buffer that can be read by the microprocessor when the leading edge of the stop bit is detected. The UART will then signal that a data character is present via a data ready status bit in a status register, when the midpoint of the stop bit occurs. The data ready signal can also be programmed to generate an interrupt.