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Non-Overlapping Clock Generator

IP.com Disclosure Number: IPCOM000061024D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Hosoya, Y Kumagai, M [+details]

Abstract

This article describes a non-overlapping clock generator which is used for an LSSD (Level Sensitive Scan Device) latch that was developed to raise the circuit testability. The LSSD latch is a master/slave-type latch, and two kinds of non-overlapping clocks (B-CLK, C-CLK) are required. These non-overlapping clocks have been generated by the circuit shown in Fig. 1. However, it has the following shortcomings: (1) Too many gates are required. (2) The circuit is insufficient for EMI (Electromagnetic Interference). (3) As it does not have a feedback circuit, it is possible that the overlapping between B-CLK and C-CLK happens due to the variation of rise/fall time caused by the load condition. Fig. 2 shows the circuit configuration of the new non-overlapping clock generator that resolves the above problems.