Browse Prior Art Database

Short Channel FET Fabrication

IP.com Disclosure Number: IPCOM000061057D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Brodsky, MH [+details]

Abstract

A short channel FET is fabricated employing a thin film thickness to define the gate or channel length. In the figure, a thin film transistor (TFT) is shown fabricated with Si, either amorphous, polycrystalline, or single crystal, as the active region with the channel whose conductance is controlled by a gate voltage VG in combination with a source-to-drain bias VDS = VD-VS A STEP, VERTICALLY OR SLOPED, IS ETCHED IN A MULTILAYER STACK OF thin films. The FET is built along the edge of the step using film thicknesses to define the channel length. The gate length is defined by a film thickness. In the figure, VS, VD and VG are, respectively, the source, drain and gate voltages and are applied to the electrodes shown. The device is built by first making a blanket deposit of the insulator I1 onto the substrate.