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Branch-Processing Instruction Cache

IP.com Disclosure Number: IPCOM000061062D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Cocke, J Grohoski, GF [+details]

Abstract

This article teaches a novel instruction fetching mechanism designed for computer architecture which processes branch instructions while fetching other instructions, thereby eliminating most of the so-called branch penalty. The figure depicts the organization of the mechanism. It consists of an instruction cache, a directory integral with the cache arrays, and associated branch processing logic and dataflow which assumes the existence of a fixed-point processing unit and a floating-point processing unit to which non-branch instructions will be shipped. For the purposes of illustration, the instruction cache is logically organized as a 2-way set associative, 8KB capacity, 64B linesize cache. The instruction cache spans four physical arrays; each one is organized as 128 x (128 + directory bits + special function bits + parity).