Browse Prior Art Database

Power Sequence Independent Expansion Bus Interface

IP.com Disclosure Number: IPCOM000061090D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Dang, LQ Grazier, EC Keller, PR [+details]

Abstract

Computer systems may expand or add auxiliary hardware by connecting an external unit to the host system. In systems where the external unit is directly attached to the host system's I/O bus, faults in the expansion unit may propagate to the host system, making the host system inoperative. A circuit is provided which logically disconnects the external bus in the external I/O unit from the local bus in the host system when either a host system reset or an I/O unit power fault occurs. The host may also disconnect from the external bus under program control. Facilities are provided which allow the host system to test the state of the external bus lines. The drawing is a diagram of the expansion bus interface. The output of latch 2 on I/O Reset line 17 controls gate 3 and provides a reset signal to the external unit.