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Binary Arithmetic Subtraction Using Full Adder Without Carry Input

IP.com Disclosure Number: IPCOM000061091D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
West, RM [+details]

Abstract

A simple binary arithmetic subtractor logic circuit includes a full adder without carry input, at least one of whose inputs for subtraction is inverted and whose output for subtraction is also inverted. The simple circuit (Fig. 1) comprises a first inverter 1 whose input is a multi-bit binary number X in twos complement form. The inverter 1 inverts the bits of the number X to provide one input to a full adder 2 whose other input is a multi-bit binary number Y in twos complement form. The output of the adder 2 is to a second inverter 3 which inverts the bits of the number output by the adder 2 to give the output X-Y. In twos complement form, binary numbers can be positive or negative, the most significant bit being used as a sign bit.