Browse Prior Art Database

Improved Systems Timing Using a Pseudo-Edge-Triggered Shift Register Latch

IP.com Disclosure Number: IPCOM000061095D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Jeremiah, TL Ng, CS Nosowicz, EJ [+details]

Abstract

In a conventional level sensitive scan design (LSSD) having a latch- trigger design, L1 latches feed directly into L2 latches. The L2's feed combinatorial logic, which then feeds the L1's. Often, the L1 is fed directly from its own L2 for the purpose of holding data in a pipeline structure. In a purely hazard-free design, the L1's and L2's would be fed by independent non-overlapping clocks. This creates a severe timing penalty because pulse cycles must be adjusted to account for late data arriving from the longest combinatorial path. Failure to do this would cause wrong data to the L1's to be latched because the data in a long path could arrive at the latch after its clock has become inactive. In high performance designs, the L1, L2 clocks are overlapped.