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Multisource Interrupt Vector Generation and Acknowledgement

IP.com Disclosure Number: IPCOM000061103D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Marshall, JR [+details]

Abstract

A system is provided for identifying an interrupt, in a microprocessor system, in which a vector, representing the interrupt, includes the interrupt level and the interrupt states of all interrupt sources at that interrupt level. Thus, the microprocessor receives an interrupt input which includes the level of the interrupt so that the interrupt acknowledgement is directed to the appropriate level. This system minimizes both hardware and code time requirements. The present embodiment assumes a level sensitive microprocessor interrupt system of M levels (m1, m2, m3, etc.). The level identification is encoded within an interrupt vector of V bits. Due to hardware constraints, X (X > 0) vector bits must be in a predetermined state.