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Epitaxial Configuration for Low Leakage Ser-Tolerant Silicon Material

IP.com Disclosure Number: IPCOM000061178D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Chakravarti, S Garbarino, P Varano, MF [+details]

Abstract

A retarding electric field barrier for minority carriers, diffusing from an Si substrate, is created via an ion-implanted/epitaxially grown Player on a standard P- (11-16 ohm-cm) substrate. The barrier reduces the high temperature bulk diffusion leakage as well as the alpha particle sensitivity of field-effect transistor (FET) memory devices The field strength is dependent on the impurity concentration gradient between the P+ layer and the P- substrate. High interstitial oxygen concentration (0i < 1018/cm3) in Czochralski-grown Si wafers often leads to SiOx precipitation in the active device regions. Controlled oxygen precipitation by means of heat treatment of Si wafers results in high leakage currents at elevated temperature (- 45ŒC).