Data Detector and Clock Recovery Circuit for Dibit (2,8) Code
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
A detector for the dibit (2,8) code, having at least three clock cycles between transitions (other than those comprising dibits) and constraints on runs of closely spaced dibits, is described. The constraints on runs of closely spaced dibits in the (2,8) code are described on pages 507-509. To reproduce input data, the proposed data detector uses the characteristics which distinguish dibits (i.e., transitions written in adjacent clock cells) from all other data patterns. The dibit readback signal will be smaller than the readback signal for all other code patterns, and will be shifted with respect to clock periods.