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Full Function Series/1 Instruction Set Emulator

IP.com Disclosure Number: IPCOM000061194D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Parker, TE Veneski, GA [+details]

Abstract

This emulator is designed to be an optional attachment to a single chip microprocessor which executes a subset of the full IBM Series/1 instruction set. The emulator allows the remainder of the Series/1 instruction set to be implemented via execution of instructions residing in an attached auxiliary storage chip. When an instruction is encountered which is not part of the native instruction set of the microprocessor, the auxiliary storage emulator is activated. The instruction emulation takes place in auxiliary storage in order to provide fully transparent emulation. The drawing shows the interconnected address and data flow between the auxiliary storage, the microprocessor and the microprocessor main storage. The following design considerations had to be taken into account: 1.