Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
This article describes a technique of array testing whereby the tester will make frequency measurements for array performance and determine failure signatures. The disclosed technique can reduce tester complexity by allowing simple DC (level) tests to be substituted for high accuracy transient (time) testing. It will also allow better process monitors, make testing easier by replacing some delay testing with frequency testing, and allow for implementation on-chip with little or no overhead (less than 0.05%). The address valid (AV) input is a system signal that defines when the address and data are valid at the chip. This signal sets the latch circuit which is reset by either a read complete (RC) or a write complete (WC) signal. This signal also latches the address and data that are presented to the array.