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Mask Design (Pseudo Matrix) for Automatic Inspection Disclosure Number: IPCOM000061199D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09

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Branz, H Buettner, S [+details]


To eliminate rejects resulting from faulty masks during the production of integrated semiconductor memories, each mask 1 (Fig. 1) is produced twice adjacent to each other enlarged 5 or 10 times. Then, both masks 1 are compared in an automatically operating unit. If they are identical and thus non-faulty, they are reduced by optical projection means 2 and used to selectively illuminate two photoresist-coated semiconductor chips. To permit using the optical projection means 2 even if it is no longer capable of reducing the two compared masks for illuminating two chips without image defects, a memory chip 4 (Fig. 2), laid out symmetrically to a center area 3, is processed as follows. Only one enlarged mask 4 is produced for the chip. On the right and left of mask 4, one mask half 4a', 4b', including a center area 3', is produced.