Browse Prior Art Database

Partial Result Duplication

IP.com Disclosure Number: IPCOM000061201D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Finney, DW [+details]

Abstract

In some processors, the data flow including General Purpose Registers (GPRs), Arithmetic Logic Unit (ALU), System Registers, etc., are byte sliced to eliminate as many chip boundary crossings as possible. This is due to driver/receiver delays being considerably greater than internal logic gate delays. In a representative byte slice processor, only shifted data or carries (internal in the ALU) must cross chip boundaries. Typically, only a limited set of instructions both shift data and require an arithmetic function to be performed on this data, such as Multiply First Step (MFS), Multiply Step (MPS), Divide Step (DVS), and Shift Left One then Add (SLOA). Therefore, all other instructions have only one-chip boundary crossing in the worst-case dataflow path.