Browse Prior Art Database

Synchronizing Error Reporting and Recovery

IP.com Disclosure Number: IPCOM000061204D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Scott, EK Wong, BB [+details]

Abstract

Two loosely-coupled programmed units, such as a host processor and a programmable peripheral control unit, are synchronized in the error detection and recovery for peripheral devices attached to the control unit. In certain conditions, if the control unit detects an error and logs it within the control unit, subsequent events can cause a loss of the reported error. Error reporting to the host is delayed until the host missing-interrupt handler (MIH) detects the problem such that the peripheral subsystem error is never lost. In cached peripheral subsystems, a peripheral device works with a semiconductor cache. Data transfers occur between the device and the cache. During such asynchronous transfers, an error condition may occur in the device to prevent further activity of the device in the subsystem.