Data Bypass Methodology for a Performance Pipeline Processor
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
Efficient utilization of arithmetic logic unit (ALU)-generated data in a pipeline processor is maintained when the target register is also the source of the next instruction. A central processing unit (CPU) may be designed as a pipeline processor. Such a processor may be organized so that while the result of instruction #1 is being stored away in the general-purpose registers (GPR write cycle), instruction #2 is being executed in the ALU (Execute cycle), the data associated with instruction #3 is being accessed from the general-purpose registers (GPR read cycle), and instruction #4 is being accessed from main storage (Fetch cycle).