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Pulsed ECL Decoder

IP.com Disclosure Number: IPCOM000061227D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Wernicke, FC Wong, RC [+details]

Abstract

While conventional emitter-coupled logic (ECL) decoders are very fast, their power consumption becomes prohibitive when considered for use with denser designs, such as large clocked arrays. The pulsed ECL decoder scheme here described proves very effective in reducing ECL decoder power in such applications at only a slight delay penalty. Fig. 1 shows an ECL decoding scheme for an 8 T 256 decode application. Pulsing circuits are shown in Figs. 2 and 3. ECL decoder power reduction is achieved in this manner: 1) Each true/complement (T/C) generator and word driver current are clocked. 2) A speed-up capacitor is added to each decoder circuit. 3) Decoder circuit resistor values are increased. Referring to Figs. 2 and 3: During Standby, all outputs of the T/C generators are held low.