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Store/Write Structure for Static Rams

IP.com Disclosure Number: IPCOM000061240D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Aichelmann, FJ Flaker, RC [+details]

Abstract

A technique is described for improving the performance of a memory array chip by providing the means for storing single through block stores for static RAMs (random-access memories) without requiring a preceding fetch ("prefetch") cycle. A static RAM chip is presently required in high performance memory array applications to satisfy performance requirements. For such applications, the static RAM chip must have similar functional characteristics to those of a dynamic RAM, namely a "page-mode-like" transfer mechanism of more than one data transfer from the array chip. Fig. 1 illustrates a basic functional block diagram for such a RAM chip, including the structure for avoiding "prefetch" for partial stores. Elements 9, 10, 11 and 15 in Fig. 1 are the principal on-chip additions necessary to implement this scheme. Fig.