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Using a Common Barrel Shifter for Operand Normalization, Operand Alignment and Operand Unpack and Pack in Floating Point

IP.com Disclosure Number: IPCOM000061260D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Finney, DW Olsson, B [+details]

Abstract

This article describes an arrangement wherein the chip area required to implement independent functions in a floating-point processor is reduced by using common logic. When two separate floating-point processors are implemented in a single silicon gate process (SGP) chip, maximum efficient utilization of chip area is necessary. It has been determined that three independent functions required by both processors have a common characteristic. The three functions (operand normalization, operand alignment, and operand unpack and pack) involve a shifting operation of some sort or another. Therefore, a common, general-purpose barrel shifter can be used to implement these functions. Operand normalization involves a shift left of / to 63 bits. The operand first will feed some random logic and generate shift left count.