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Using the Exponent ALU As an Extension to the Mantissa ALU for Bcd-To-Binary and Binary-To-Bcd Conversion in Floating Point

IP.com Disclosure Number: IPCOM000061266D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Finney, DW Olsson, B [+details]

Abstract

This article describes an arrangement wherein the amount of logic required to implement in binary-coded decimal (BCD)-to-binary and binary-to-BCD conversions is reduced without a performance penalty in floating-point arithmetic by concatenating the exponent and mantissa ALUs (arithmetic and logic units). When two separate floating-point processors are implemented in a single silicon gate process (SGP) chip, maximum efficient utilization of chip area is necessary. In order to perform a BCD-to-binary or a binary-to-BCD conversion, a 76-bit ALU is required. The floating point processor, however, only has a 16-bit exponent ALU (EALU) and a 68-bit mantissa ALU (MALU).