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Low Power, High Performance, Complementary FET-DTL and FET Logic Circuits

IP.com Disclosure Number: IPCOM000061275D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Klimanis, V Montegari, F Swietek, D [+details]

Abstract

This article concerns the design of general-purpose logic circuits for gate arrays in which n-type and p-type FETs (field-effect transistors) are employed to better the performance at low power obtainable from DTL (diode-transistor logic) circuits operating with a single supply voltage. A typical DTL circuit employing a collector load resistor is shown in Fig. 1. A complementary FET-DTL logic circuit in which p-type FETs T1 and T2 replace the collector load resistor is shown in Fig. 2. The push-pull drive provided by this circuit yields better performance on high capacitance nets. The source and drain terminals of T1 and T2 are connected in parallel and the gates of each tied to an input node to act as a logical negative OR.