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Dynamically Configured Redundant Bus Structure Disclosure Number: IPCOM000061280D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09

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Beilstein, KE [+details]


A redundant bus structure is described wherein M lines plus at least one redundant line are connected to M plus at least one shift register along with a shift register control (SRCL) or toggle line. If M lines are required between a microprocessor and a circuit macro, the shift registers select only M of the M plus at least one redundant line for connection between the microprocessor and the circuit macro. This redundant bus structure may be employed where: 1. A bus has a limited number of interfaces to circuit macros. 2. At each circuit interface, the logic is added to configure the bus. 3. An intelligent control unit or processor P is available to exercise and test each line and to apply algorithms for configuring the bus. The figure shows a bus structure going to the interface of a single typical macro.