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Low Power FET DTL NOR

IP.com Disclosure Number: IPCOM000061291D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Klimanis, V Montegari, F Swietek, D [+details]

Abstract

This article describes a general-purpose logic circuit for gate arrays in which p-type FETs (field-effect transistors) are used as active pull-ups to perform a NOR function, with a resulting high performance and low power consumption. The DTL (diode-transistor logic) NOR function is similar to two, one-way DTL NAND circuits with dotted collectors, which produce a two-way NOR. A power saving is achieved with this circuit by the use of a complementary FET-bipolar NOR combined with a unique base drive resistor configuration.