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Automatic Synthesis of I/0 Wire Areas

IP.com Disclosure Number: IPCOM000061318D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Lleonart, G [+details]

Abstract

A technique is described whereby input/output (I/O) port wiring of very large-scale integrated (VLSI) circuit chips is maximized through the use of an automatic synthesis computer program. With the advent of large multiple plane VLSI chips, storage requirements to process chip wiring have increased tremendously. As a result, it is extremely difficult, if not impossible, to wire a large VLSI chip in one operation using a typical "maze runner" program. As a result, methods have been developed that segment the chip so as to allow a wiring program to process the segments separately, then joining the segments together at the end of the program. The technique described herein provides a method of processing I/O areas in a modular manner.