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Bus Design in a High Capacitance Environment

IP.com Disclosure Number: IPCOM000061330D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Hanna, JT Zimmerman, JP [+details]

Abstract

A bus design is described which allows CMOS drivers to drive high speed signals in a high capacitance environment. Normally, a trade-off exists between speed and capacitive loading when CMOS technology is used to drive logic signals. In the bus environment shown in Fig. 1, the unmultiplexed address/ data lines AD(O-7) tend to be very popular signals. They are used by memory, the microprocessor, I/O devices contained within the unit, and by any externally attached devices. Capacitance is relatively large on these lines since each component using these signals adds a capacitive load, and the additional board wiring also adds capacitance. The switching speed of a CMOS gate is a function of the capacitive load on the gate's output.