Method to Generate an Automatic Wait-State During Direct Memory Access
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09
A method is described to automatically include a wait state during direct memory access (DMA) transfers to satisfy the standard I/O device access timings without the need for external wait signal generation. In a bus environment for a Personal Computer (PC) where all I/O read and write cycles are 5 clock cycles long (as opposed to 4 clock cycles for memory accesses), DMA cycles which perform an I/O cycle concurrent with a memory cycle must also be 5 clock cycles long. The IBM PC and PC XT use the 8237 DMA controller chip to perform DMA transfers. The 8237 normally only allows 3 clock cycles for a DMA transfer, with an input signal (+READY) used to extend this transfer cycle.