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Partitioning of Video Memory for Improved CPU Access

IP.com Disclosure Number: IPCOM000061335D
Original Publication Date: 1986-Jul-01
Included in the Prior Art Database: 2005-Mar-09

Publishing Venue

IBM

Related People

Authors:
Shore, AB [+details]

Abstract

A technique is described whereby a video memory, as used in buffer circuitry of cathode ray tube (CRT) graphic adapter circuitry, is partitioned so as to provide greater access to a computer's central processing unit (CPU). In prior art, CPU accesses to video memory were interspersed among the CRT refresh memory accesses at a ratio of one CPU access to five or more CRT accesses, resulting in delays in buffer updating. The technique described herein provides a significant increase in CPU access through the use of memory partitions. Control logic, as shown in the block diagram, is provided first to determine if the CPU address in partition is being scanned. If it is, then the CPU cycle is held for a regular interspersed cycle. If it is not, determination is made to see if the next partition is to be scanned.